Search Results for "model train design"

This is a work in progress split-flap display. Each module can flip between 40 unique characters: letters, numbers, and a few symbols. Multiple modules fit perfectly alongside each other to build bigger displays. The primary design goal was to make something that's possible to fabricate at home in small or single quantities and can be customized and built by an intermediate hobbyist at a reasonable price. This meant using widely available materials and avoiding any tooling with a high...

...Built around an ESP32 PICO-D4 microcontroller, a 1.3″ 240×240 ST7789 display and MPU6050 inertial sensor, the device allows you to build a “floating hologram” style display module with additional networked visual features like weather display or follower counts. The hardware design includes versions of the PCB (Naive version, Ironman version) and 3D model files for the enclosure (3D printed or CNC metal). The software leverages LVGL (a GUI library for microcontrollers) and supports surface touch or IMU-based input. Because it connects via WiFi/Bluetooth, it can fetch live data and display dynamic content, bridging embedded display, network, and interactive gadget design.

A cryptoprocessor is a processor that does not do or use any encryption or decryption (thus escapes US export controls), but which works natively on encrypted data and code. Almost any encryption is possible, including "none at all". The trick is that a computer famously and happily takes garbage in and puts garbage out, just as happily as it does "2+2=4", so all we have to do is change our OWN idea of what is garbage and what is sense and the computer will remain happy but we then have a...

This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips The code here is no longer up to date. The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5% logic registers.