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...Working:
- Activation of asynchronous and synchronous smart cards
- Exchanging data with supported Smart card (Sending / Receiving)
- Asychron T=0 APDU communication.
- Basic sychron communication
- ETU calculation from TS byte.
- Support class for SLE4432 / SLE4442 / SLE4441 and SLE4440 compatible sychron smartcards.
Mostly used for secure data storage.
Open points:
- Error handling not completly implemented.
No retries if parity error is found.
- Setup of communication parameters from ATR
- T=1 communication not supported (Still possible via "raw" sendBytes(..) / receiveBytes(..))
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips
The code here is no longer up to date.
The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5%...