Search Results for "order"

Chipyard is a framework and generator for constructing custom RISC‑V SoC hardware. Built at UC Berkeley, it leverages Chisel/FIRRTL to generate full-stack systems—from CPU cores to peripherals—and includes simulators, FPGA deployment tools, and integration with Rocket Chip and other RISC‑V ecosystems.

Rocket Chip is a parameterized RISC-V SoC generator written in Chisel that produces synthesizable RTL for a wide range of cores and configurations. At its heart is the Rocket core, a simple, in-order, five-stage RISC-V implementation, but the generator composes much more: coherent caches, MMUs, interrupt controllers, and buses via the TileLink interconnect. A diplomacy framework (LazyModules) lets designers wire components with negotiated parameters, enabling reuse and rapid exploration of different cache sizes, port counts, and memory hierarchies. ...

Gizzard is a Scala framework originally developed by Twitter for building scalable, fault-tolerant, distributed key-value stores that can be sharded and replicated. It provides infrastructure for routing requests through shard trees, splitting or rebalancing shards dynamically, failover, and migrations. In Gizzard, data is stored in underlying storage shards (which could be databases or other stores) and Gizzard handles the process of routing requests correctly as the cluster topology...