Search Results for "cpu simulate"

Chipyard is a framework and generator for constructing custom RISC‑V SoC hardware. Built at UC Berkeley, it leverages Chisel/FIRRTL to generate full-stack systems—from CPU cores to peripherals—and includes simulators, FPGA deployment tools, and integration with Rocket Chip and other RISC‑V ecosystems.

...It was created to measure full HTTP request processing instead of only route matching speed. The project runs small real HTTP servers for many stable frameworks and tests a simple /hello endpoint. It can add configurable handler delay to simulate business work such as database calls, cache access, disk writes, socket activity, or microservice calls. The benchmark uses wrk and scripts to collect throughput, latency, allocation, concurrency, pipelining, and CPU-bound results. It is useful for developers who want repeatable framework comparisons that better reflect end-to-end web request behavior.

This project includes C source code for generic CPU tests tailored for testing in the safety domain according to IEC 61508. Additional to the test programs, the project includes a test framework consisting of a program calling the sub-test-programs and a TCL script which injects faults to verify the test programs. To run the TCL script, a user has to set up a testbench with Modelsim to simulate the HDL code of a CPU.