Search Results for "chip"

...Built at UC Berkeley, it leverages Chisel/FIRRTL to generate full-stack systems—from CPU cores to peripherals—and includes simulators, FPGA deployment tools, and integration with Rocket Chip and other RISC‑V ecosystems.

Rocket Chip is a parameterized RISC-V SoC generator written in Chisel that produces synthesizable RTL for a wide range of cores and configurations. At its heart is the Rocket core, a simple, in-order, five-stage RISC-V implementation, but the generator composes much more: coherent caches, MMUs, interrupt controllers, and buses via the TileLink interconnect.

...It can control and transmit SMBus/I2C, GPIO, Clock and other interfaces through USB. The product includes software and hardware. It has the characteristics of easy use and development. The core chip is CP2112 Graphical software and operating manual can be downloaded for free at http://xbridge-m01.doidx.com Provide the underlying Java API, http://xsmbus-m01.doidx.com , which can do simple testing and develop user-specific graphical interface products. xSmbus-xx, xBridge-xx do not need to install the driver according to the operating system in advance, nor select the COM port requirement, as long as they are in the Java environment, they can be plug and play. ...

...Runtime is optimized with NEON, OpenCL and Hexagon, and Winograd algorithm is introduced to speed up convolution operations. The initialization is also optimized to be faster. Chip-dependent power options like big.LITTLE scheduling, Adreno GPU hints are included as advanced APIs. UI responsiveness guarantee is sometimes obligatory when running a model. Mechanism like automatically breaking OpenCL kernel into small units is introduced to allow better preemption for the UI rendering task. Graph level memory allocation optimization and buffer reuse are supported. ...

...Mongoose OS is integrated and powers many types of devices and appliances globally. Microsoft Azure IoT recommends Mongoose OS for OTA, automatic device management and deploying firmware updates at scale. Built-in flash encryption, crypto chip support, ARM mbedTLS optimized for small memory footprint. Device management dashboard service. Supported microcontrollers are CC3220, CC3200, ESP32, ESP8266, STM32F4, STM32L4, STM32F7. Recommended dev kits are ESP32-DevKitC for AWS IoT, ESP32 Kit for Google IoT Core.

...This repository mainly focuses on enabling monitor mode and frame injection on many chips. A real Wi-Fi jammer that allows to overlay ongoing frame transmissions with an arbitrary jamming signal. It uses the Wi-Fi chip as a Software-defined Radio to generate jamming signals. It allows using non-standard channels such as 80 MHz bandwidth in the 2.4 GHz bands. It allows to set of arbitrary transmission powers. It allows patching the D11 core's real-time MAC implementation. It allows to extract of CSI of up to 4x4 MIMO transmissions at 80 MHz bandwidth.

Weeno is an software-only extension of Wiring / Arduino for potentially all and any Atmel AVR MCUs. And potentially all chip architectures from all companies, whether Freescale, SiLabs, TI, even ARM. Basically, the goal is to make AVR-Weeno, ARM-Weeno, 8

ELCO stands for Embedded Lisp COmpiler or Esdens Lisp COmpiler. The goal is to create a lisp compiler for embedded 32bit architectures. (i.e. ARM) With this compiler you are able to write lisp code on a naked chip. No OS needed.