Open Source VHDL/Verilog Formats and Protocols

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VHDL/Verilog Formats and Protocols

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Browse free open source VHDL/Verilog Formats and Protocols and projects below. Use the toggles on the left to filter open source VHDL/Verilog Formats and Protocols by OS, license, language, programming language, and project status.

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  • 1

    Anie

    PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e

    Embedded system design (VHDL description) based on Xilinx's Spartan3E Development Kit to perform real-time PID control and monitoring of time critical plants such as brushless DC motors, maglevs... vimeo.com/channels/anie prezi.com/gpbycavq499c/anie/
    Downloads: 0 This Week
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  • 2
    the goal of this project is to build a stack for Lonworks Protocol and device working on this protocol
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  • 3
    This is an image coder with fixed sampling, at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with res. up to 352x288).
    Downloads: 0 This Week
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  • 4
    The OS561 operating system based around FORTH/Java. The OS is to run on a VHDL chip OpenHardware design called the Minon, but could become available for other platforms. The unique point of the design is a revolutionary data compression technology.
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