Search Results for "digital logic simulator"

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Showing 1 open source project for "digital logic simulator"

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    PHDL

    PHDL

    An HDL alternative to PCB graphical schematic capture tools.

    PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic...
    Downloads: 0 This Week
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