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Top Apps

  • The First VoIP Communications Cloud in the World The First VoIP Communications Cloud in the World Icon
    The First VoIP Communications Cloud in the World Icon

    The Smarter Business Phone Solution

    • Powerful Unified Communication Features
    • Fast, Easy, Free Setup & Install
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  • Communicate & Connect with Ring Central's VoIP Solution Communicate & Connect with Ring Central's VoIP Solution Icon
    Communicate & Connect with Ring Central's VoIP Solution Icon

    Cloud Powered Business Phone System

    • Unrivaled value & reliability in one solution
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  • ghdl-updates

    GHDL - a VHDL simulator

    GHDL is the leading open source VHDL simulator. *** Now on github.com/tgingold/ghdl *** We have binary distributions for Debian Linux, Mac OSX and Windows. On other systems, getting GHDL from here means downloading the current source package and building GHDL from source. Alternatively you can get the latest source version (warning : occasionally unstable!) by pulling a snapshot from the git repository.

  • adms Icon

    adms

    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git

  • Controlix Icon

    Controlix

    An operating system written in RTL

    The Controlix operating system is written in RTL and is designed to be modular, synchronous, distributed, verifiable and retargetable.

    Downloads: 1 This Week Last Update: See Project
  • Cereon

    A new 64-bit RISC platform, complemented by a set of development tools, standards specifications and synthesizable VHDL implementations.

    Downloads: 0 This Week Last Update: See Project
  • PLP

    Powerfull pre-processor

    Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)

    Downloads: 0 This Week Last Update: See Project
  • SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

    Downloads: 0 This Week Last Update: See Project
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