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cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips
The code here is no longer up to date.
The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5%...
Sisolo is a simple solar logger, meant to run on small embedded devices, like routers. Currently it targets OpenWrt, uses Yasdi to interface with SMA inverters and Curl to store logs on an ftp server.
Simple Lossless Ad-hoc Protocol (SLAP) is designed to be used for wireless digital data transfer on embedded systems. The program is built for uClinux, a derivative of Linux designed for embedded microcontrollers, but can be easily ported.