Search Results for "stage"

This project is now in the research and development stage. It is intended for very small microcontrollers with a single processor and represent simple multithreading kernel what written by C language. Is planning create implementations for AVR8 and STM8, may be. Now it is suspended until better time.

This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips The code here is no longer up to date. The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5%...

...A key design objective is to use as little dedicated hardware as possible for communication between nodes in the network, and to be able to adapt the network topology in real-time so as to minimize the occurrence of collisions between packets. To achieve this, a protocol has been designed specifically for the task, and implemented in assembler for AVR microcontrollers. The project is currently at the stage of testing the protocol for bugs and implementing some simple devices which use it.