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Showing 1 open source project for "blocks"

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    cMIPS

    cMIPS

    cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core

    ...The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5% logic registers.
    Downloads: 0 This Week
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