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cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips
The code here is no longer up to date.
The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5%...
Alexandria is an archive system for large data amounts. Suitable for inhomogenous collections of books, media files, art items and other artifacts. Main focus is on easy usage, small executable file and portability.
Keep Contactin' is an advanced address book for Windows Mobile Smartphones and Pocket PCs. It's fast and PIM.VOL-independent. If you are a coder, designer, architect, tech writer please JOIN US NOW! Let's create the best software together!