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This parser has been developed for those who wants to develop his/her own tool around VHDL RTL. Only synthesizable subset of VHDL is supported and it may not work for machine/tool generated VHDL files. This parser has been developed in Java in order to make it platform independent. It reads RTL and populates its internal object model. There are APIs to extract the design information from the database, APIs to elaborate the design along with expression evaluation capabilities. ...

This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the...

vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.

Verilog 2005 synthesizable subset parser built on ANTLR framework. 3-nov-2014: latest release here: https://github.com/gburdell/parser

The PARSEC CEE is the primary achievement of several years of effort at NASA's Marshall Space Flight Center. The CEE was developed to allow engineers in the Advanced Concepts Department to rapidly prototype launch vehicle and spacecraft concepts.

A GDSII database parser and stream integrity verifier