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  • 1

    System Verilog Parser IEEE 1800 LRM

    IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API

    This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities.
    Downloads: 0 This Week
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  • 2

    Free VHDL Parser with Java, Python and T

    IEEE VHDL-93 LRM supported parser implemented in Java, APIs Python/Tcl

    This parser has been developed for those who wants to develop his/her own tool around VHDL RTL. Only synthesizable subset of VHDL is supported and it may not work for machine/tool generated VHDL files. This parser has been developed in Java in order to make it platform independent. It reads RTL and populates its internal object model. There are APIs to extract the design information from the database, APIs to elaborate the design along with expression evaluation capabilities. ...
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  • 3
    vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy.
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  • 4
    Spider PCB

    Spider PCB

    Hierarchical Schematic and PCB

    This project is in a pre-alpha stage and is intended to give a rough idea about the final program. It does not do much more than draw pretty pictures. Hierarchical circuit layout is commonplace amongst IC designers, but Spider PCB brings hierarchical layout to the PCB industry. Not only is the schematic hierarchical, but also the layout. Ever wanted to lay out a 16-band equaliser, with 5 sound channels? Lots of copying and pasting on the PCB-side. Just imagine if you could lay out one...
    Downloads: 0 This Week
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  • 5
    naga EDA devotes to provide useful electronic design tools in C++ and, especially, Python. The current release contains naga.Verilog, a Verilog parser. Please visit project homepage http://naga-eda.org for more information
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    Downloads: 13 This Week
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  • 6
    vMAGIC
    vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
    Downloads: 0 This Week
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  • 7
    Verilog 2005 synthesizable subset parser built on ANTLR framework. 3-nov-2014: latest release here: https://github.com/gburdell/parser
    Downloads: 0 This Week
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  • 8
    A GDSII database parser and stream integrity verifier
    Downloads: 0 This Week
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  • 9
    FERMAT's SystemC Parser using Doxygen and Xerces-C++ XML
    Downloads: 0 This Week
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