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... and the Wishbone bus are supported. However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1.

Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)

A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.

vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.

SHELLEY Software HardwarE Light LanguagE Yep !