Open Source Server Operating Systems Electronic Design Automation (EDA) Software

Electronic Design Automation (EDA) Software for Server Operating Systems

Browse free open source Electronic Design Automation (EDA) software and projects for Server Operating Systems below. Use the toggles on the left to filter open source Electronic Design Automation (EDA) software by OS, license, language, programming language, and project status.

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  • 1
    MMTL, the Multilayer Multiconductor Transmission Line 2-D and 2.5-D electromagnetic modeling tool suite, generates transmission parameters and SPICE models from descriptions of electronics interconnect dimensions and materials properties.
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    Downloads: 17 This Week
    Last Update:
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  • 2
    adms
    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
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    Downloads: 6 This Week
    Last Update:
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  • 3
    IC CAD tools, documentation, scripts, and libraries for designing high-performance ICs, including SUE for schematics, MAX for layouts, DPC for datapaths and MCC for megacells. Prebuilt binaries for Linux, Sparc-Solaris, and HP-PA.
    Downloads: 4 This Week
    Last Update:
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  • 4
    KFilter is an application to design acoustic hifi loudspeakers in a theoretical way. It provides an interactive analysis of the equivalent analogue circuit design.
    Downloads: 1 This Week
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  • 5
    Capsim(r) C Text Mode Kernel(TMK),DSP and communication blocks, topologies, libraries and tools for the development of high performance block diagram digital signal processing and communications systems,built in interpreter for scripting.SystemC support.
    Downloads: 0 This Week
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  • 6
    This is an IEEE 1532 compliant JTAG programmer for CPLDs, FPGAs and similar programmable logic devices. It is only starting; developers are welcome!
    Downloads: 0 This Week
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  • 7
    The comprehensive C++ library MGEN for IC layout and connectivity comes with the X11/Motif full custom layout editor PARIS and the powerful waveform viewer/processor MANIAC. Industry proven, it is the basis for layout generators, placers, routers etc.
    Downloads: 0 This Week
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  • 8
    Design and implementation of silicon and software for baseband processors conforming to IEEE wireless standards. Initial focus on WiMAX and WiFi.
    Downloads: 0 This Week
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  • 9
    Resistor Value Identifier

    Resistor Value Identifier

    Identify electronic resistor values

    This HTML utility allows the user to select standard color codes or surface mount numbers, then it identifies the resistor value. There is no need to memorize color codes or multipliers. An online working example of this program can be used at ZoomAviation.com/programs.
    Downloads: 0 This Week
    Last Update:
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  • 10
    Sigschege will be a software to create timing diagrams for digital electrical circuits.
    Downloads: 0 This Week
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  • 11
    An online SSL (128-bit strong encryption) repository for scripts created and maintained by Synopsys Design Consultants.
    Downloads: 0 This Week
    Last Update:
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  • 12
    A portable loudspeaker design system supporting measurement, modeling, simulation and optimization of boxes, filters and systems.
    Downloads: 0 This Week
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  • 13
    An Arduino pseudo OS with a focus on data acquisition and control.
    Downloads: 0 This Week
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  • 14
    ePnR

    ePnR

    ePnR is an IC block standard cell placement & routing tool

    ePnR is a simple Integrated Circuit (IC) block standard cell placement & routing tool. ePnR currently supports only circuit blocks using equal height standard cells arranged in one or more channels of user configurable length. Standard cells are described in a simple text based library (compliant with eLogSim). Placement follows initially the cell call order in the SPICE like circuit input netlist. However, a placement optimization, aiming at minimum weighted accumulated wire length, by simulated annealing is available. Routing consists of channel routing as first step. If un-routed connections are left, Maze routing can (optionally) be applied. ePnR does not guarantee completely finished routing. However, un-routed connections will be left with rubberband connections and marked start and end points for subsequent manual routing using a third party layout editor. ePnR outputs in CIF 2.0 and GDS stream format readable by e.g. the free KLayout editor.
    Downloads: 0 This Week
    Last Update:
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