Search Results for "re-tools"

Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API...

...SimFPGA elaborates the project files using GHDL and builds the VHDL project before simulating it. This ensures code verification without the need for additional compilation tools. If an error is detected in any of the project files during elaboration or simulation, a message is displayed in the console indicating the type and location of the error, allowing the user to quickly resolve it.

naga EDA devotes to provide useful electronic design tools in C++ and, especially, Python. The current release contains naga.Verilog, a Verilog parser. Please visit project homepage http://naga-eda.org for more information

ReliaFree is a Python and PyGTK based suite of tools to assist in Reliability, Availability, Maintainability, and Safety (RAMS) analyses. ReliaFree is intended to be an Open Source alternative to proprietary RAMS analyses solutions.

PyPCB is a Python package for working with PCB (http://pcb.sourceforge.net) files. PyPCB can be used to create new useful tools, as footprint generators or library managers.

pyLPCTools is a replacement for the Flash Programming Tools use with the Philips(tm)/NXP(tm) LPC2xxx series of ARM based microcontrollers. pyLPCTools is a script together with some ARM assembly language and a Python user interface. Please Donate !!

GerbTool is a set of tools for modifying gerber and excellon drill files. GerbTool can be used to tile multiple gerber files as a single job, and can be run interactively or in batch mode.