Search Results for "bus"
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Showing 3 open source projects for "bus"
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IP-XACT 2009/2014 Platform
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . -
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My Beaglebone Black Project
show and configure
...It is intended to demonstrate the interaction of software with hardware and to encourage the development of peripheral hardware that works with the software described here. The presented tablet Beaglebone Black is to be extended by the display of industrial bus protocols such as CANbus, Profibus, Profinet, etc. -
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This (Python) tool allows you to easily create FPGA bitfiles for your embedded system, from several Open Source IPs (compatibles with the OpenCores Wishbone bus) . It will also generates the corresponding drivers (currently only Linux ones).
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