Showing 8 open source projects for "student management system java source code"

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  • 1

    System Verilog Parser IEEE 1800 LRM

    IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API

    This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the...
    Downloads: 0 This Week
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  • 2
    Penthode

    Penthode

    Penthode simulates, draw and plot electrical power distributions

    Given a simple net-list describing the high level power architecture of your system Penthode: - simulates the voltage and current from device turn on to the steady state. - highlights components working out of specification - draws a nice power tree diagram showing the currents/powers balance - plots node transient voltage and gate current waveforms It is possible to change component parameters interactively to improve the design
    Downloads: 0 This Week
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  • 3
    Qfsm

    Qfsm

    A graphical Finite State Machine (FSM) designer.

    A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
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    Downloads: 8 This Week
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  • 4
    Generic packet visualization tool for generating flow diagrams from formatted logs. Can be used for cache coherency diagrams, software interaction diagrams or to plot network communications.
    Downloads: 0 This Week
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  • 5
    Netsim is a mobile ad hoc network simulator targeted at large heterogeneous node configurations. It is written in Java and is easily extensible through its modular concept.
    Downloads: 8 This Week
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  • 6
    A java based digital logic simulator, designed to be used as an educational tool. uses a GUI to allow users to quickly and easily create and visualise circuits from simple components. User can create custom components
    Downloads: 1 This Week
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  • 7
    vIDE is a cross-platform tool for writing and simulating Verilog models. It provides user friendly project management and file editing, integrated simulation engine, waveform viewer, pre-compiled modules, and many other cool features.
    Downloads: 0 This Week
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  • 8
    NecJGui is an antennas design tool, interface for Numerical Electromagnetic Code. It allows easily making NEC input files, and viewing them in 3D. It also contains a version of the simulator, so it's complete IDE for full-wave EM simulation.
    Downloads: 0 This Week
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