Search Results for "java runtime environment"

UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So,...

SVEditor is an Eclipse-based IDE (Integrated Development Environment) for SystemVerilog and Verilog files. It features syntax coloring, content assist, source indent and auto-indent, and structure display.

DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code

Analog Insydes is a Mathematica toolbox for symbolic analysis of analog electronic circuits. This project provides a set of free add-ons to Analog Insydes, including a Java front-end and a native netlister for Cadence's Analog Design Environment (ADE).

Jove - The Open Verification Environment for the Java (TM) Platform

mcuStudio is a development environment for Microcontrollers. It's based on Eclipse (plugin). The aim is to provide a high quality development environment for electronics. First editions will target Microchip Pic mcu's. Other mcu will be supported later.

EDAEd is Java-Based applications to demonstrate aspects of EDA (Eletronic Design Automation). This tools aim to help students of this area to view in a pratical environment, basic tools for placement and routing and data structures envolved.

jEDA IDE (Java Eletronic Design Automation Integrated Development Environment) is a multiplatform, open-source tool used for electrical circuit design, schematic capture, simulation and prototyping.

LogicS is an EDA (Electronic Design Automation) desktop program, targeting digital circuits: designing, edtiting & simulating them. The user will be provided with a user-friendly environment for doing this (adding logic gates, creating links, simulating)