Search Results for "structural engineering"
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Showing 4 open source projects for "structural engineering"
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VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.
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Gnetman is primarily a netlist translator, capable of translating between formats such as VHDL, Verilog, and SPICE. Only structural gate-level netlists are supported. Various netlist manipulations are supported.
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s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.
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The Verilog Construction Toolkit is a C++ library which provides the ability to read in, create and or modify verilog cell-based structural netlists.
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