Search Results for "data analysis"

Qucs is a circuit simulator with graphical user interface. The software aims to support all kinds of circuit simulation types, e.g. DC, AC, S-parameter, Transient, Noise and Harmonic Balance analysis. Pure digital simulations are also supported.

Java Quine McCluskey (JQM) implements the Quine-McCluskey algorithm with Petrick’s Method for minimizing Boolean functions. Designed for both education and industrial application, it handles up to 16 variables and functions. Uniquely, JQM bridges the gap between theory and practice: it visualizes the solution process with generated Karnaugh Maps for students, while supporting PLC engineers by exporting results to Structured Text (ST) and Ladder Diagram (LD). The software includes a GUI for...

The developed graphical interface is based on the SKILL language which is a Lisp dialect used as a scripting language and PCell (Parameterized Cells) description language used in many EDA software suites by Cadence Design Systems.

The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types, such as logic analyzers, MSOs, oscilloscopes, multimeters, LCR meters, sound level meters, thermometers, anemometers, light meters, dataloggers, function generators, power supplies, GPIB interfaces, and more.

A GTK+/Gnome2 graphical front end for the IW3HEV Vector Network Analyzer, also has a signal generator, and It displays graphicaly SWR, Phase, Return Loss, X impedance, Serial resistance, |Z| Impedanze, and Inductance, and capacitance.

decida is [de]vice & [ci]rcuit [d]ata [a]nalysis. It is used for electron device characterization, procedural simulation/analysis of electronic circuits, or more general data analysis tasks.

An automatic 2D Delaunay mesh generator and solver for Finite Element Analysis. Can solve 2D field problems (Poisson and Helmholtz Equations). Can use LAPACK/ARPACK solvers producing OpenGL/Postscript output. Uses C/GTK/GTKGLExt/MFC. Runs on Win32/Unix.

A static timing analysis program written in C++. Cadence LEF/DEF definitions of circuit geometry and SDF definitions of circuit timing data of a synchronous circuit are compiled in order to generate timing constraints for non-zero skew circuit operation.