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Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
...One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed.
Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog .
It has Tcl/Python API support.
ipxact2verilog - Generate Verilog module from IP-XACT definition
ipxact2vhdlentity - Generate VHDL entity from IP-XACT Component definition
verilog2ipxact - Generates IP-XACT definition from Verilog modules
vhdl2ipxact - Generates IP-XACT definition from VHDL source
ipxactcoherencycheckerverilog / ipxactcoherencycheckervhdl - Validates IP-XACT Component definition with RTL
validateipxact - IP-XACT Linting tool
DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code
Libraries, documentation, examples & drivers for Eagle Technology South Africa's Data Acquisition products. These include ISA, PCI, PCI Express, USB, Serial & Ethernet. Supported languages will be C/C++, JAVA, Perl, Python.
Modelio-Open is a project hosting a set of open source extensions (SoaML, SysML and UML Testing Profile) for a previous version (1.2) of the Modelio Free tool .
Currently, the lastest version (2.x) of Modelio modeling and generation tool is available at http://modelio.org/downloads/download-modelio.html. All extensions are downloadable at http://forge.modelio.org/projects.
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Processes boolean functions which can be provided either as a list of 0s and 1s or which can be provided as a formula in first-order logic (using disjunctive or conjunctive normal forms). Internally the Quine McCluskey algorithm is used.
The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.
A clearing house for various pieces of open source software which use the GenCAM data format for input or output of electronic interconnect (PWB, PCB, PWA, PCA) information.