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HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
Generic packet visualization tool for generating flow diagrams from formatted logs. Can be used for cache coherency diagrams, software interaction diagrams or to plot network communications.
Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms.
Silicis is a new formal framework for designing [verification] algorithms.
mcuStudio is a development environment for Microcontrollers. It's based on Eclipse (plugin). The aim is to provide a high quality development environment for electronics. First editions will target Microchip Pic mcu's. Other mcu will be supported later.
IslandEv distributes a Genetic Algorithm (like <a href="/projects/jaga">JaGa</a>) across a network (see <a href="/projects/distrit">DistrIT</a>) using an island based coevolutionary model in which neighbouring islands swap migrating individuals every
mCon aims to be platform independent, complete IDE for micro controller development. The project will use Eclipse as its foundation and the initial goal is to support development for the microchip PIC microcontrollers.
CircuitSmith is to be a comprehensive electronic design package being developed in Java which will include schematic capture, printed circuit board layout and any other features which I (and hopefully others) can be bothered to program.
GNU PIC LIBRARY PROJECT
The interest of this project is to develop a set of Libraries that are released in LGPL License to use to PIC microcontroler programming.
Then any program resulted by this use would be a proprietary or free softwares.
A clearing house for various pieces of open source software which use the GenCAM data format for input or output of electronic interconnect (PWB, PCB, PWA, PCA) information.
vIDE is a cross-platform tool for writing and simulating Verilog models. It provides user friendly project management and file editing, integrated simulation engine, waveform viewer, pre-compiled modules, and many other cool features.
This project aims at providing Open Source tools for the development and the verification of SystemC/TLM (Transaction Level Modeling) IP models, and at promoting their use by embedded software developers on SoC (System-On-Chip).