Open Source Java Electronic Design Automation (EDA) Software

A multiplatform vector drawing program with a complete library of electronic symbols. Schematics and drawings are stored in a very compact text format. There is no netlist concept behind the drawings (so no simulation, and this is a choice) but this allows a great graphical flexibility and ease of use, making FidoCadJ the perfect tool for exchange sketches in forum and newsgroup discussions with a few clicks. Drawings can be exported in several graphic formats, such as pdf. Follow the development live on Twitter: https://twitter.com/davbucci

JMCAD is an program for the modeling and simulation of complex dynamic systems. This includes the ability to construct and simulate block diagrams. The visual block diagram interface offers a simple method for constructing, modifying and maintaining complex system models. The simulation engine provides fast and accurate solutions for linear, nonlinear, continuous time, discrete time, time varying and hybrid system designs. With JMCAD, users can quickly develop software or "virtual" prototypes of systems or processes to demonstrate their behavior prior to building physical prototypes. The user builds his system model by selecting predefined blocks from a block library and simply wiring the blocks together. Each block of the diagram performs a function. Users can also create custom blocks in Java and add them to the JMCAD block library. JMCAD is a block diagram language for creating complex nonlinear dynamic systems.

The DigitalSimulator is your Virtual Electronics Lab, allowing you to design, simulate and output your digital circuit board designs.

Circuitmod is a circuit simulator that extend the capacity of the original Falstad's Java Circuit Simulator into CMOS Chips, Led Arrays, Led Matrix and PIC Programming. The Horizon is limitless. Try today.

Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.

DLD V 2.0 Released Digital Logic Design is a Software tool for designing and simulating digital circuits. It provides digital parts ranging from simple gates to Arithmetic Logic Unit. You may start your circuit from simple gates and flipflops and keep on converting them into ICs. These ICs, later on, may be incorporated into other circuits to built more complex circuits like CPU. You may even use SOP expressions to generate digital circuits in IC form. You can use this software to design Combinational, Synchronous and Asynchronous Sequential Circuits. The circuit working can be analyzed by using output parts like LEDs, Seven Segment Display as well as CRT and digital Oscilloscope all provided in the software. This Software may be used by professionals, hobbyists and students alike. The teachers may incorporate this software in their courses like Digital Logic and Computer Design, Computer Architecture, Computer Organization and Embedded Systems.

ImageToGerber makes it easy to convert any image to gerber files, ready to send to a PCB manufacturer. More info at: https://www.imagetopcb.com Demo video: https://youtu.be/HUvt0mOHv_M Forget about spending long hours etching and drilling at home, or learning to use complicated CAD software, schematics, layout design,… And more importantly, ImageToPCB is more than just a converter, it expands the potential of your design or image. It unlocks the possibility to easily make improvements and updating your design, as you will be able to make design modifications, add a silkscreen layer, resize drill diameters, create a soldermask layer to protect copper areas and to avoid accidental shorts, convert a single-side design into a double-side or multi-layer design,… all that just by editing your image with your preferred image editor.

SVEditor is an Eclipse-based IDE (Integrated Development Environment) for SystemVerilog and Verilog files. It features syntax coloring, content assist, source indent and auto-indent, and structure display.

Visually build boolean logic circuits and then simulate their operation. Create custom components from user-designed circuits. Written in Java for cross-platform functionality. NOTE: This project has moved to Bitbucket at http://bitbucket.org/kwellwood/circuitsandbox

TimeDoctor is a tool to visualize execution traces of tasks, queues, cache behavior, etc. While originally targeting embedded media processors and includes specific features for analyzing audio/video streaming applications it has wider applicability.

Libraries, documentation, examples & drivers for Eagle Technology South Africa's Data Acquisition products. These include ISA, PCI, PCI Express, USB, Serial & Ethernet. Supported languages will be C/C++, JAVA, Perl, Python.

Java Quine McCluskey implements the Quine McCluskey algorithm with Petrick’s Method (or the method of prime implicants) for minimization of Boolean functions. This software can be used both for learning and solving real problems. As a learning/teaching tool, it presents not only the results but also how the problem was solved as well as how to use Karnaugh Maps to solve the problem. Up to sixteen functions of sixteen variables can be minimized. A graphical interface is provided for entering and editing the truth table that can be saved and loaded. The results can be exported in HTML format. It generates the Karnaugh Map for educational purposes and the actual truth table from the obtained expressions even when multiple solutions for each function are found. This implementation supports PLC programming, so results can be presented in many forms including Structured Text (ST) and Ladder Diagram (LD) along with conventional Boolean expression.

This project provides a analog / mixed signal IC schematic capture and layout tool with the accompanying netlisters, simulators, and verification tools.

1. Comes with 200+ high level Tcl commands around SoC platform assembly 2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity database with advance queries 8. Hierarchy Manipulation to create Power Domain, Voltage Domain, comply with Floor planning 8.a. Insert new hierarchy 8.b. Remove existing hierarchy 9. Associate the IP-XACT memory maps with the SoC component instances 10. Dump out the C Model for the entire design 11. Glue-Logic insertion 12. Spare port insertion across hierarchies 13. Automatic creation of the top module and it's ports based upon specified rule 14. Creates stub module

The PARSEC CEE is the primary achievement of several years of effort at NASA's Marshall Space Flight Center. The CEE was developed to allow engineers in the Advanced Concepts Department to rapidly prototype launch vehicle and spacecraft concepts.

Netsim is a mobile ad hoc network simulator targeted at large heterogeneous node configurations. It is written in Java and is easily extensible through its modular concept.

DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code

A Java API for manipulation of GDSII stream data. It is intended to provide a useful, reusable and platform independant library for CAD/CAE application developers. This API Requires the Java Backus-Naur Test API (JBNT). You may download it from: ht

PIC Development Studio is a simulator for the PIC16F84 microcontroller. It also provides a plugin framework making it possible to develop custom components. A library of ready-made components is included.

Modelio-Open is a project hosting a set of open source extensions (SoaML, SysML and UML Testing Profile) for a previous version (1.2) of the Modelio Free tool . Currently, the lastest version (2.x) of Modelio modeling and generation tool is available at http://modelio.org/downloads/download-modelio.html. All extensions are downloadable at http://forge.modelio.org/projects.

The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.

The aim of this project is to develop a GDSII viewer by using Java programming language. Efforts will be made especially on ease-of-use, efficiency, and capacity.

Power consumption analysis tools for embedded systems. MARTE to AADL model transformation with ATL for tools interoperability. More info on the project at http://sourceforge.net/apps/trac/lab-sticc/

bel_fft is a FFT co-processor that can calculate FFTs with arbitrary radix. It is a hardware implementation of the free software Kiss FFT ("Keep it simple, Stupid!"). The target was to allow a simple replacement of the software code with the hardware implementation. Therefore bel_fft comes with a software driver that is compatible with the Kiss FFT routines. bel_fft also has a modular architecture and allows interfacing different bus architectures. So far AMBA AXI, Altera's Avalon bus and the Wishbone bus are supported. However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1.

Ycad is a library of CAD functions in Java. Currently only DXF is supported for reading, viewing and writing. The DXF drawing may be rendered to a Graphics object for printing or imaging.