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DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code
Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
TimeDoctor is a tool to visualize execution traces of tasks, queues, cache behavior, etc. While originally targeting embedded media processors and includes specific features for analyzing audio/video streaming applications it has wider applicability.
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool.
We are currently on version 2.1 of the tool. We have created an eclipseplugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool.
VHDL revolutionized how FPGA designs and digital logic circuits have been designed and captured and overcame many of the difficulties associated with the use of schematic editing tools. ...
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RegMapDef is a project to provide an XML schema and associated tools to support a standardized way of describing register maps.
The tools shall incorporate XSL style sheets and scripts to generate documentation, header files, implementation stubs etc.