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Framework for the Analysis and Modification of EDIF netlists (FAME) is a C++ framework, developed at Politecnico di Torino, aimed at automating the analysis and modification of complex circuit netlists described in the standard EDIF 2.0.0 language.
This is a simple viewer for the ``Stream Format'' for CALMA GDSII CAD libraries (``GDS II'', ``.gds'' or ``.sf'') with a couple of limitations. The main functionality is viewing the library layers with different colors.
The Virtual Electronics Library, or VE-Lib, is a C++ library used to easily add electronic simulation in your programs. It makes use of the scripting language Lua to easily add new components like new resistors and microchips.
Digital Signal Processing Block Diagram Compiler - user extendable to all DSP's, but presently supports only the TI C2000 family. Rich support for fixed point arithmetic, both saturated and unsaturated. Block diagram entry is via TinyCAD (included).
Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
GEZEL is a cycle-based hardware description language. The GEZEL tools offer stand-alone - and cosimulation, and code-generation into VHDL code. User-defined library-block extensions in C++ allow to add new cosimulation/cosynthesis interfaces.
Mixed Analog/Digital Simulator framework - parser and elaborator for Verilog and Verilog-AMS, and an extended C++ (ParC - http://parallel.cc) to be used as the simulation engine.
audacity-extra now provides a sleek dark themed version of the Audacity open source sound editor. The project experiments with Audacity variations. There's a vowel-sound target-practice display for language learners and an analog waveform data logger for embedded systems.
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cad-utils is a set of modules for designing electrical boards.
These programs allow you to cut and place graphs which used to
present the models of the original electrical schemes.
Libraries and sample code for accessing remote toolpath delivery services such as VoluMill. Although much of the code is specific to the VoluMill service, it also defines open standards for exchanging toolpath information, parameters, and geometry.
libLCS is a hardware description library in C++ aiming to be as powerfull and easy as the Verilog HDL. It currently supports logic gates, flipflops, clock, and facilitates delays, continuous assignments and variable value dumping into VCD files.
The comprehensive C++ library MGEN for IC layout and connectivity comes with the X11/Motif full custom layout editor PARIS and the powerful waveform viewer/processor MANIAC. Industry proven, it is the basis for layout generators, placers, routers etc.
Hierarchical VCD Viewer is new trace file viewer. It's based on Qt 3.3.4 (migrating to Qt 4.1) graphic library and its main feature is to provide a hierarchical view of VCD trace file.
Microdev is a complete development tool dedicated to microcontroller based boards. It is composed of a graphical and real time simulator and a full featured editor supporting Picbasic, JAL and Asm.
ChNIDAQ allows user programs to use the NI-DAQ Clibrary and run interpretively without compilation. It is an ideal solution for teaching and learning data acquisition, prototyping, and web-based remote data acquisition.
The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.
This is an ECAD toolkit for building programs and scripts to solve problems encounter in chip design.It currently addresses the layout, circuit and logic design areas.
toolbox with information and programs for Computer Aided Innovation
The scientific background of Skidbladnir is known as the Theory of Inventive Problem Solving; in English abbreviated as TIPS or TRIZ, in German as TRIS.
ESOMA is a component orientated framework for simulation and evaluation
of arbitrary microprocessor and DSP architectures. Simulators using
ESOMA are runtime configurable. Architectural changes do not need
recompiling. Programming language is C++ (Linu