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Showing 2 open source projects for "verilog code"

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    adms
    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
    2 Reviews
    Downloads: 7 This Week
    Last Update:
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  • 2

    EduCPU

    Simple CPU for education

    This is a simple CPU design, written in Verilog, intended for educational purposes. The objective is to provide a simulatable processor where the source code exposes concepts in CPU microarchitecture.
    Downloads: 0 This Week
    Last Update:
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