Make your own virtual FPGA system and profile deeply with CI.
TestDrive Profiling Master is a free simulation software for Verilog/SystemVerilog and C/C++. It supports a CI (Continuous Integration) activity for H/W & S/W engineers' cooperation. Run by MS Windows environment, its use is governed by MIT License(Profiles) and LGPLv3(TestDrive Profiling Master). Based on the powerful compiler Verilator and GCC, TestDrive Profiling Master provides a totally free virtual FPGA system environment with various dynamic documents for profiling in deep on your system design. It performs a seamless conversion to a real FPGA environment without any changes of your testing software. I hope you will accomplish a successful design with TestDrive Profiling Master. Q&A : email@example.com
Java class profiler
Minimalistic java profiler using instrumentation and asm libs to preform a measure of the time spent by methods. Mesure is efficient until the micro second and very realistic on milli second. The ui allows exports, remote connection and multiple connections.
CxxProf is a manual instrumented Profiling library for C++
Please take a look at our project wiki for more detailed information: https://github.com/monsdar/CxxProf/wiki/What-is-CxxProf%3F
At an early stage of development. Application/middleware usage monitoring/reporting. Focus on business transactions/use cases to help communicate with users. Small footprint, easy to use GUI and a level of statistical analysis to summarise the data.
latrace is frontend for the glibc 2.4+ LD_AUDIT feature
A .NET CRL Profiler. Allow to profile .NET managed applications storing data into a SQL Server Express Database.