RISC-V BOOM
SonicBOOM: The Berkeley Out-of-Order Machine
The riscv-boom project (also called BOOM or SonicBOOM) implements a high-performance, synthesizable out-of-order RISC-V core written in the Chisel hardware construction language. It targets the RV64GC (i.e. 64-bit with general + compressed + floating point) instruction set and supports features such as virtual memory, caches, atomics, and IEEE-754 floating point. The design is parameterizable, meaning users can tune pipeline widths, buffer sizes, functional units, and other microarchitectural knobs to explore tradeoffs. It is capable of booting Linux and running standard benchmarks, and its performance (measured in CoreMarks/MHz) is competitive with commercial cores. The project is intended primarily for hardware/architecture research and teaching, rather than production silicon, and typically is used in conjunction with SoC frameworks (for example via Chipyard) to integrate BOOM into larger systems.