A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
A graphical viewer and editor that allows browsing and creating of "infopages". These infopages are xml pages structured according to a specification created specifcally for the IDTV platform