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XLS is an open-source toolkit for building high-level hardware with a modern compiler stack that spans from a functional DSL to optimized IR and hardware generation. At the front end, DSLX lets you describe algorithms with strong typing and familiar control flow while remaining synthesis-friendly. The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for...
A simple framework for plugin system development with as few dependencies as possible. It is designed to offer a set of very lean classes (plugin managers and plugin interfaces) which can easily be customised by decoration or inheritance.
Yapsy v1.x supports Python2 and Python3. Its source package contains versions of the sources for both pythons.
Yapsy v2+ supports Python 3 and it's development happens now on https://github.com/tibonihoo/yapsy/
Usage samples, advices and...
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.