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VHDL Design Tool - code generation and project management
Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation.
TreeDL (Tree Description Language) is a notation for tree structures used by programs (like syntax trees) and tool for translation of tree descriptions to target programming language, docs generation, etc. Tool's functionality can be extended by plugins.