2 projects for "stack" with 2 filters applied:

  • Build Secure Enterprise Apps Fast with Retool Icon
    Build Secure Enterprise Apps Fast with Retool

    Stop wasting engineering hours. Build secure, production-grade apps that connect directly to your company’s SQL and APIs.

    Create internal software that meets enterprise security standards. Retool connects to your business data—databases, APIs, and vector stores while ensuring compliance with granular permissions and audit logs. Whether on our cloud or self-hosted, build the dashboards and admin panels your organization needs without compromising on security or control.
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  • Outgrown Windows Task Scheduler? Icon
    Outgrown Windows Task Scheduler?

    Free diagnostic identifies where your workflow is breaking down—with instant analysis of your scheduling environment.

    Windows Task Scheduler wasn't built for complex, cross-platform automation. Get a free diagnostic that shows exactly where things are failing and provides remediation recommendations. Interactive HTML report delivered in minutes.
    Download Free Tool
  • 1
    Material Tailwind

    Material Tailwind

    Easy-to-use components library for Tailwind CSS and Material Design

    Material Tailwind is an open-source library that uses the power of Tailwind CSS and React to help you build unique web projects faster and easier. The stunning design inspired by Material Design is a bonus. Enhance your workflow with seamless integrations for your favorite tools using Material Tailwind.
    Downloads: 2 This Week
    Last Update:
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  • 2
    XLS

    XLS

    XLS: Accelerated HW Synthesis

    XLS is an open-source toolkit for building high-level hardware with a modern compiler stack that spans from a functional DSL to optimized IR and hardware generation. At the front end, DSLX lets you describe algorithms with strong typing and familiar control flow while remaining synthesis-friendly. The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA/ASIC flows. ...
    Downloads: 2 This Week
    Last Update:
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