Search Results for "simulation"

...The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA/ASIC flows. A key idea is “software-style” iteration: fast, deterministic simulation via the JIT encourages test-driven development and property checking before committing to RTL. XLS also provides tooling for pipelining, state insertion, and formal equivalence checks between different stages, giving developers confidence as designs evolve. ...

...HiPS tool has also functions of static/dynamic analysis : T-invariant detection, Reachability path analysis, deadlock state detection, and k-boundedness analysis. In addition, it is possible to perform a random walk simulation with each firing steps.

A highly customizable theme for vim and Neovim with support for lsp, treesitter and a variety of plugins. Tabline is tabby.nvim and status line is feline.nvim. You can find my config for tabby and feline here as well as the auto-generated highlight groups here. If you would like a single consumable file that contains that can be added to your own config check out misc/feline.lua and misc/tabby.lua.

The riscv-boom project (also called BOOM or SonicBOOM) implements a high-performance, synthesizable out-of-order RISC-V core written in the Chisel hardware construction language. It targets the RV64GC (i.e. 64-bit with general + compressed + floating point) instruction set and supports features such as virtual memory, caches, atomics, and IEEE-754 floating point. The design is parameterizable, meaning users can tune pipeline widths, buffer sizes, functional units, and other...

A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.

The Simulation Interoperability Standards Organization (SISO) [http://www.sisostds.org] has developed a standard XML schema for representing simulation federation engineering agreements. This project is an editor for creating federation engineering documents compliant with that schema.

bts es un programa para convertir aplicaciones java (.jar) a una aplicacion windows (.exe) Es de codigo abierto y cualquiera lo puede modificar

...Access Road offers the out-of-the-box simulations of GNU/Linux Ubuntu® (components and rights on the file system), MySQL Server®, and a generic Role-Based-Access-Control application to adapt to your needs. It is designed for database, system, and application administrators, IT architects and developers, auditors. Access Road provides a full simulation of MySQL Server. This includes the components, the users, the hosts and the privileges at any level. The focus is on IT weak configurations, executing environments (malware analysis) and people authorizations. Reliability and the ability to explain the results are the main objectives. A 80 pages tutorial is provided. A powerful framework allows new simulations to be added. ...

The Xholon project explores: software as systems of linked nodes, organized hierarchically. The Xholon toolkit supports this back-to-basics approach, and demonstrates practical benefits through examples from numerous domains.

This is a tool developed by 2nd yr CSE B.Techs at IIT Guwahati.We have designed a software in C++ language which,given some design specifications of an analog amplifier generates a netlist file in the current folder which can be opened in LTSpice.

The Distributed Real-time Embedded Analysis Method (DREAM) is a tool and method for the real-time verification and performance estimation of distributed real-time embedded (DRE) systems. Publications: http://www.ics.uci.edu/~gabe/publications.html.

Daxi is an aplication for simulating and designing operating systems scheduling algorithms for processes and IO scheduling.

Charmy is a tool for specification of Software Architectures through diagrammatic, UML-based notations, and validation of the architectural specification conformance with respect to functional requirements.

A threat modeling tool based on FreeMind

Simulation of a simple factory building cars. The aim is to design and refactor the code according to some semi-precise specification.

...This process leads to locally inhomogeneous material properties of the manufactured components. By integrating these specific material properties of the SLM-process into a topology optimization, product developers can be supported in the design process by simulation. For this purpose, a topology optimization method is being developed which takes into account the unique material properties of parts manufactured with the SLM-process. In this homepage, the generation of a material database as well as the development of the topology optimization method is introduced and the impact on the component design is presented. ...