Search Results for "numerical simulation software"
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Showing 16 open source projects for "numerical simulation software"
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XLS
XLS: Accelerated HW Synthesis
...At the front end, DSLX lets you describe algorithms with strong typing and familiar control flow while remaining synthesis-friendly. The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA/ASIC flows. A key idea is “software-style” iteration: fast, deterministic simulation via the JIT encourages test-driven development and property checking before committing to RTL. XLS also provides tooling for pipelining, state insertion, and formal equivalence checks between different stages, giving developers confidence as designs evolve. ... -
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Nightfox
A highly customizable theme for vim and neovim with support for lsp
A highly customizable theme for vim and Neovim with support for lsp, treesitter and a variety of plugins. Tabline is tabby.nvim and status line is feline.nvim. You can find my config for tabby and feline here as well as the auto-generated highlight groups here. If you would like a single consumable file that contains that can be added to your own config check out misc/feline.lua and misc/tabby.lua. -
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HiPS : Hierarchical Petri net Simulator
HiPS tool features to design and analyze hierarchical Petri nets
HiPS tool is developed at the Department of Computer Science and Engineering, Shinshu University, which is a tool design and analysis of Petri nets, developed using Microsoft Visual C # and C++. HiPS tool has a way of intuitive GUI which enable hierarchical and/or timed-net design. HiPS tool has also functions of static/dynamic analysis : T-invariant detection, Reachability path analysis, deadlock state detection, and k-boundedness analysis. In addition, it is possible to perform a random... -
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RISC-V BOOM
SonicBOOM: The Berkeley Out-of-Order Machine
The riscv-boom project (also called BOOM or SonicBOOM) implements a high-performance, synthesizable out-of-order RISC-V core written in the Chisel hardware construction language. It targets the RV64GC (i.e. 64-bit with general + compressed + floating point) instruction set and supports features such as virtual memory, caches, atomics, and IEEE-754 floating point. The design is parameterizable, meaning users can tune pipeline widths, buffer sizes, functional units, and other... -
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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FEAT Editor
Editor for SISO standard compliant federation agreements
The Simulation Interoperability Standards Organization (SISO) [http://www.sisostds.org] has developed a standard XML schema for representing simulation federation engineering agreements. This project is an editor for creating federation engineering documents compliant with that schema. -
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bts es un programa para convertir aplicaciones java (.jar) a una aplicacion windows (.exe) Es de codigo abierto y cualquiera lo puede modificar
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Access Road
Simulator of access controls
The Access Road software is a universal simulator of access controls that is intended to improve design and auditing of IT security. Access Road offers the out-of-the-box simulations of GNU/Linux Ubuntu® (components and rights on the file system), MySQL Server®, and a generic Role-Based-Access-Control application to adapt to your needs. It is designed for database, system, and application administrators, IT architects and developers, auditors. -
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The Xholon project explores: software as systems of linked nodes, organized hierarchically. The Xholon toolkit supports this back-to-basics approach, and demonstrates practical benefits through examples from numerous domains.
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This is a tool developed by 2nd yr CSE B.Techs at IIT Guwahati.We have designed a software in C++ language which,given some design specifications of an analog amplifier generates a netlist file in the current folder which can be opened in LTSpice.
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The Distributed Real-time Embedded Analysis Method (DREAM) is a tool and method for the real-time verification and performance estimation of distributed real-time embedded (DRE) systems. Publications: http://www.ics.uci.edu/~gabe/publications.html.
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Daxi is an aplication for simulating and designing operating systems scheduling algorithms for processes and IO scheduling.
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Charmy is a tool for specification of Software Architectures through diagrammatic, UML-based notations, and validation of the architectural specification conformance with respect to functional requirements.
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Simulation of a simple factory building cars. The aim is to design and refactor the code according to some semi-precise specification.
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SLM-Topo
Topology optimisation designed for laser based additive manufacturing
In the selective laser melting process (SLM), components are built up layer by layer by incremental melting of metal powder with a laser beam. This process leads to locally inhomogeneous material properties of the manufactured components. By integrating these specific material properties of the SLM-process into a topology optimization, product developers can be supported in the design process by simulation. For this purpose, a topology optimization method is being developed which takes into...
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