Search Results for "control flow graph"
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Showing 1 open source project for "control flow graph"
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XLS
XLS: Accelerated HW Synthesis
XLS is an open-source toolkit for building high-level hardware with a modern compiler stack that spans from a functional DSL to optimized IR and hardware generation. At the front end, DSLX lets you describe algorithms with strong typing and familiar control flow while remaining synthesis-friendly. The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA/ASIC flows. A key idea is “software-style” iteration: fast, deterministic simulation via the JIT encourages test-driven development and property checking before committing to RTL. ...
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