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Our Free Plans just got better! | Auth0
With up to 25k MAUs and unlimited Okta connections, our Free Plan lets you focus on what you do best—building great apps.
You asked, we delivered! Auth0 is excited to expand our Free and Paid plans to include more options so you can focus on building, deploying, and scaling applications without having to worry about your security. Auth0 now, thank yourself later.
The regex-centric, fast lexical analyzer generator for C++
A C++ high-performance regex library and Flex-compatible lexical analyzer generator with full Unicode support, new indentation anchors, lazy quantifiers, and many other modern features. Accepts Flex lexer specification syntax and is compatible with Bison/Yacc parsers. Generates reusable source code that is easy to understand. Supports fast scanning of UTF-8/16/32 files, strings, and streams. The reflex scanner generator generates clean C++ lexer class code that is thread-safe. Generates...
Flora-2 is a powerful knowledge representation and reasoning system designed for building knowledge-intensive applications. It is based on F-logic, HiLog, Transaction Logic, and also supports defeasible reasoning. Applications include intelligent agents, Semantic Web, ontology management, and more.
If you use Flora-2 and like it, please acknowledge it in your project!
An HDL alternative to PCB graphical schematic capture tools.
...We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool.
VHDL revolutionized how FPGA designs and digital logic circuits have been designed and captured and overcame many of the difficulties associated with the use of schematic editing tools. We believe the use of an HDL is also the way of the future when it comes to PCB design.
The PHDL compiler automatically supports the output of PADS and Eagle netlists, and through extending a simple java class, users can generate a netlist in practically any format required by their choice of a layout tool.
Hipo is a hypothetical computer to facilitate the learning of machine language. The student can use hipo to develop simple programs and understand the internal logic of a computer. There is a plan to implement Donald Knuth's MMIX machine language, also.
Jeeg is a dialect of Java based on a declarative
synchronization mechanisms.Synchronization constraints in Jeeg are
expressed in a linear temporal logic. Jeeg is inspired by the current
trend in aspect oriented languages.
Our goal was to develop a very simple programming language for expressing state machines. You can express the logic of a fairly complex, real life state machine in a single page of text that is easy to understand. Creates Java (C++ may be next).