Mixed Analog/Digital Simulator framework - parser and elaborator for Verilog and Verilog-AMS, and an extended C++ (ParC - http://parallel.cc) to be used as the simulation engine.
Berkeley Yacc is an LALR(1) parser generator. Berkeley Yacc has been made
as compatible as possible with AT&T Yacc. Berkeley Yacc has been extended
to generate Python, Perl and Java code.