Search Results for "zebra design 3"

...MANOOL is meant to compare and compete directly with Python, PHP, Ruby, Perl, and Tcl, although incidentally it has some combination of unusual features. Example: {{extern "manool.org.18/std/0.2/all"} in WriteLine[Out; "Hello, world!"]} Explicitly stated design priorities of MANOOL: 1. implementation simplicity; 2. expressive power, usability, and general utility, attention to syntax and semantics details; 3. correctness, security, and overall quality of implementation, run-time reliability; 4. run-time performance and scalability; 5. consistency, completeness, orthogonality of features, and language elegance, conceptual economy and purity. ...

APTOS is an open source Apt translator project. It consists of several CAM applications, based on the Apt programming language. It is used to create control programs for cnc mills, lathes, water jets, lasers, and other industrial equipment.

JNode is a Java New Operating system Design Effort. JNode is a simple to use and install Java operating system for personal use on modern devices. Any java application runs on it, fast and safe. See our homepage for additional information.

COOL is an object oriented programming language specialized for concurrent software development. Language syntax is similar to C++/C# and Java. For proper documentation please read the diploma thesis (Only available in german yet). Some of the goals to achieve: - Embedding some design-patterns on language level (singleton, state-pattern) - Implementation of a back-end for byte-code generation - Extending the compiler with an optimization phase for optimizing byte-code - Optimizing...

PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic...

The Wittgen programming language consists of just two instructions and one special variable name. Wittgen allows you to assign any text string to a variable of any name. It also allows you to retrieve the text assigned to that variable. Lastly, it has a special variable called “Doing Now”. Every execution step consists of retrieving the contents of Doing Now, removing the first assign found in that content and performing that assign. In the course of performing that assign any retrieve...

Mixed Analog/Digital Simulator framework - parser and elaborator for Verilog and Verilog-AMS, and an extended C++ (ParC - http://parallel.cc) to be used as the simulation engine.

Generate a parser at runtime from a collection of C++ objects. Concisely state a parser specification in ordinary C++ code. Learn from a parser generator with an object-oriented design.

This project contains a set of tools for formal verification and static analysis of VHDL design.

Modern Jass is a Design by Contract implementation for Java which uses Java 5 annotations, the Pluggable Annotation Processing API (JSR 269), the Compiler API (JSR 199), and the Bytecode Instrumentation API.

ECCO is a web-based IDE. In other words is an online development environment with file manager, console interface for compiling and execution of code and an editor with syntax highlighting, tabs and support for many languages and accessed with a browser

Extended C gives Object-Oriented features such as self-referential structure pointers via macros to C, resulting in an object-oriented style. Currently tested in gcc, we hope to stabilize it for other compilers as well, including Borland & Visual Studio.

In simple words, JEX is a redefinition of Java using an XML syntax. This allows programmers to extend their favorite language. It also simplifies compilers, IDEs and code generators. Among foreseeable extensions are UML diagrams , Design Patterns...

VHDLC is a VHDL to C++ translator aiming at full VHDL '93 compliance. It provides the translator and supporting VHDL libraries for the target host C++ compiler.