Search Results for "zebra design 3"

...MANOOL is meant to compare and compete directly with Python, PHP, Ruby, Perl, and Tcl, although incidentally it has some combination of unusual features. Example: {{extern "manool.org.18/std/0.2/all"} in WriteLine[Out; "Hello, world!"]} Explicitly stated design priorities of MANOOL: 1. implementation simplicity; 2. expressive power, usability, and general utility, attention to syntax and semantics details; 3. correctness, security, and overall quality of implementation, run-time reliability; 4. run-time performance and scalability; 5. consistency, completeness, orthogonality of features, and language elegance, conceptual economy and purity. ...

APTOS is an open source Apt translator project. It consists of several CAM applications, based on the Apt programming language. It is used to create control programs for cnc mills, lathes, water jets, lasers, and other industrial equipment.

COOL is an object oriented programming language specialized for concurrent software development. Language syntax is similar to C++/C# and Java. For proper documentation please read the diploma thesis (Only available in german yet). Some of the goals to achieve: - Embedding some design-patterns on language level (singleton, state-pattern) - Implementation of a back-end for byte-code generation - Extending the compiler with an optimization phase for optimizing byte-code - Optimizing...

FPGAsm is a low-level alternative to verilog and VHDL. A near-instant 'assembler for FPGAs', this simple yet powerful language facilitates bottom-up design, layout and wiring of modules, and generation of .xdl output. With about 10 keywords to learn, you can start making circuits in minutes. Now you can focus on learning the ins and outs of the FPGA instead of complex tools and languages. Fast turnaround time and bottom-up approach invite exploration, experimentation, live circuit...

The Wittgen programming language consists of just two instructions and one special variable name. Wittgen allows you to assign any text string to a variable of any name. It also allows you to retrieve the text assigned to that variable. Lastly, it has a special variable called “Doing Now”. Every execution step consists of retrieving the contents of Doing Now, removing the first assign found in that content and performing that assign. In the course of performing that assign any retrieve...

Mixed Analog/Digital Simulator framework - parser and elaborator for Verilog and Verilog-AMS, and an extended C++ (ParC - http://parallel.cc) to be used as the simulation engine.

Generate a parser at runtime from a collection of C++ objects. Concisely state a parser specification in ordinary C++ code. Learn from a parser generator with an object-oriented design.

VHDLC is a VHDL to C++ translator aiming at full VHDL '93 compliance. It provides the translator and supporting VHDL libraries for the target host C++ compiler.