Search Results for "support vector machine"

ALCHA aims to reduce FPGA project develop time by means of automation and abstraction, but without loosing the low-level control that HDLs, such as Verilog, provides. It will support an object oriented programming model, abstract data and signal types, and compile-time scripting.

...Generates Graphviz files to visualize state machine DFAs. RE/flex works seamlessly with Bison. Language: C++ License: BSD-3 Documentation: https://www.genivia.com/doc/reflex/html/index.html Repository: https://github.com/Genivia/RE-flex Changelog: see SF-README.md

...- Support for the Intel and AT&T syntax - An instruction renderer - An instruction parser - Instructions represented as generic models - UNIX/GNU/Linux and Windows support - Portable - written entirely in C (no external dependencies) - C++ wrapper - Supported instruction sets: MMX, 3D-Now!, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4A, AVX, AVX2, AES, TBM, BMI1, BMI2, HLE, ADX, CLMUL, RDRAND, RDSEED, FMA, FMA4, LWP, SVM, XOP, VMX, SMX, AVX-512 Source code moved to: https://github.com/swojtasiak/fcml-lib

FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.

FSMGenerator is a turn-key solution for FSM (Finite State Machine) automatic generation and integration within user`s software. Please, register to get fast personalized support. Feedbacks, feature requests and bug reports are greatly appriciated.

jRate is a real-time Java compiler and runtime system (based on GNU GCJ) with support for much of the Real-Time Specification for Java (RTSJ), including threading constructs with real-time constraints, asynchronous event handling, and memory regions.

This is an open source state machine template for C++. Initially FSM support will be given. The purpose is to facilitate developers to create state machine based C++ applications easily.