8 projects for "systemc" with 1 filter applied:

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  • 1
    SystemC Network Simulation Library (SCNSL) is an extension of SystemC to allow modelling packet-based networks such as wireless networks, ethernet, fieldbus, etc. As done by basic SystemC for signals on the bus, SCNSL provides primitives to model packet trasmission, reception, contention on the channel and wireless path loss. The use of SCNSL allows the easy and complete modelling of distributed applications of networked embedded systems such as wireless sensor networks, routers, and distributed plant controllers. ...
    Downloads: 0 This Week
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  • 2
    Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
    Downloads: 0 This Week
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  • 3
    SystemC-WMS
    SystemC-WMS (Wave Mixed Signal Simulator) is a class library that extends the standard SystemC kernel to allow modeling and simulation of complex systems comprising analog parts from heterogeneous domain (electrical, mechanical, thermal, ...).
    Downloads: 0 This Week
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  • 4

    Powersim

    Energy Estimation in SystemC.

    Power/Energy simulation in SystemC. Powersim is a SystemC class library aimed to the calculation of power and energy consumption of hardware described at system level. To this end C++ operators are monitored and different energy models can be used for each data type. Powersim does not require any change in the application source code. Current version is 0.3.0.
    Downloads: 3 This Week
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  • 5
    s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.
    Downloads: 0 This Week
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  • 6
    HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
    Downloads: 0 This Week
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  • 7
    HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
    Downloads: 0 This Week
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  • 8
    FERMAT's SystemC Parser using Doxygen and Xerces-C++ XML
    Downloads: 0 This Week
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