Clear visibility and insights into how employees work. Even remotely
Our computer monitoring software allows employees, field contractors, and freelancers to manually clock in when they begin working on an assignment. The application will take screenshots randomly or at set intervals, which allows employers to observe the work process. The application only tracks activity when the employee is clocked in. No spying, only transparency.
Take Control Of Your Contracts Without Wrecking The Budget
Ditch those spreadsheets, shared drives & crazy-expensive solutions with too many bells & whistles. ContractSafe offers the simplest way to manage your contracts efficiently without breaking the bank.
Forth interpreter for Win32.
The fastest Forth interpreter. Bilingual user interface (ru/en).
Contact e-mail: stribog24031973@gmail.com or mr.smart73@yandex.ru
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
This project was moved to https://gitlab.c3sl.ufpr.br/roberto/cmips
The code here is no longer up to date.
The VHDL model mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is an almost complete implementation of the MIPS32r2 instruction set. The TLB and assorted control registers will be included soon (as of fev 2015). The model was synthesized for an Altera EP4CE30F23. The model uses up 15% of combinational blocks and 5% logic registers.
This was a old crummy project, no longer supported. Heavily based on KolibriOS, this project was abandoned. Do not even bother to download, instead check my latest project, a challenge, completely written in NT Batch, the System Anarchist. Break the rules!