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Custom VMs From 1 to 96 vCPUs With 99.95% Uptime
General-purpose, compute-optimized, or GPU/TPU-accelerated. Built to your exact specs.
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A low-power ISA design and simulator for a 2010 IEEE competition
This is a student project designed to compete in the 2010 IEEE Computer Society Student Competition: http://www.computer.org/portal/web/competition/2010competition
The Code Red architecture is designed for extremely lower power environments, like distributed sensor networks. Included is a design of that architecture, a Java-based simulator, an implementation (without vector instructions) designed as a Logisim circuit (http://ozark.hendrix.edu/~burch/logisim/), and more.
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JEST will be the Java bytecode engineering Swiss-Army Jackhammer.
It will include a disassembler, class browser, obfuscator, optimizer, class editor, and bytecode debugger, and have an intuitive GUI.