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RARS, the RISC-V Assembler, Simulator, and Runtime, will assemble and simulate the execution of RISC-V assembly language programs. Its primary goal is to be an effective development environment for people getting started with RISC-V.
Emulator of the ancient 8 bit microprocessor SC/MP 2
Emulator of the ancient 8 bit microprocessor ISP-8A 500D/600D or more common "SC/MP" from National Semiconductor.
The download contains all sources plus an executable Java Jar file to start right away. Some SC/MP hex dump examples are provided in directory "/etc" as well.
The download also contains unit tests and some helping documentation (also in /etc).
You may slow down the CPU operations, displaying the CPUs status register as LEDs, to watch the CPU working with its registers...
nsL is a new C-like programming language for writing NSIS installation wizards (http://nsis.sourceforge.net). The nsL assembler takes nsL code and translates it into original NSIS script which can then be compiled.
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A open sourcejava card virtual machine implementation. And also some part of the VM code can be used as part of kinds of tools such as javacard bytecode disassembler.
Java Decompiler, Disassembler and Bytecode debugger. Decompiler supports Java 5 (e.g. generics, for-each loops etc). Debugger allows user to step through each bytecode and view program state. Contains Swing GUI.
jbytecode is a Java bytecode disassembler/assembler written in Python. Dissasembly code is aligned with Java bytecodes in the class file so modification and re-assembly is always possible, even when class is obfuscated.
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