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RARS, the RISC-V Assembler, Simulator, and Runtime, will assemble and simulate the execution of RISC-V assembly language programs. Its primary goal is to be an effective development environment for people getting started with RISC-V.
Emulator of the ancient 8 bit microprocessor SC/MP 2
...The emulator also contains a VDU (video display unit) output / ASCII input simulation. There are some demos in /etc. And have a look to the NIBL / TINY BASIC interpreter in the TINYBASIC folder, most of the code is over 40 years old.
Have fun,
Theo Heinrichs
A low-power ISA design and simulator for a 2010 IEEE competition
...Since the competition dictated a small team size, our professor split the class and gave each group a color. We liked the name "Code Red" and chose it to represent our team and school's color (UMass' official color is Maroon.) Only later did we realize that "Code Red" was the name of an unrelated computer worm from 2001.
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nsL is a new C-like programming language for writing NSIS installation wizards (http://nsis.sourceforge.net). The nsL assembler takes nsL code and translates it into original NSIS script which can then be compiled.
A open source java card virtual machine implementation. And also some part of the VM code can be used as part of kinds of tools such as javacard bytecode disassembler.
Java Decompiler, Disassembler and Bytecode debugger. Decompiler supports Java 5 (e.g. generics, for-each loops etc). Debugger allows user to step through each bytecode and view program state. Contains Swing GUI.
jbytecode is a Java bytecode disassembler/assembler written in Python. Dissasembly code is aligned with Java bytecodes in the class file so modification and re-assembly is always possible, even when class is obfuscated.