VHDL Design Tool - code generation and project management
Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation.
Makes using log frameworks as painless as printing to stdout by adding intentions, live templates and code inspections that support most aspects of the configured log framework. On top of this log IDs and reviews can be generated in addition.