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Showing 7 open source projects for "synopsys"
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eloomi combines Learning Management (LMS), Onboarding, Authoring, and continuous Performance Management tools in a cloud-based solution. It allows companies to optimize skill training, onboarding and employee development with strong user experience to enhance productivity and employee satisfaction. As a white label solution, the platform can be customized to mirror a company's branding and logo.
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Choose from a complete set of software solutions across EHSQ that address all aspects of top performing Environmental, Health and Safety, and Quality management programs.
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SVUnit
Systemverilog Unit Test Framework
SVUnit is a unit test framework for developers writing code in systemverilog. Verify systemverilog modules, classes and interfaces in isolation with SVUnit to eliminate bugs before they infest your design! -
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*** NOTE: as of Sept 2012, Synopsys is no longer using this project to update GNU Toolchain and Linux kernel for DesignWare ARC processors. Open Source Software for DesignWare ARC processors has been moved to github at: https://github.com/foss-for-synopsys-dwc-arc-processors
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ASDM-NoC
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks
... testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation) -
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This is the public release of code for the Synopsys Ottawa SNUG presentation "ICC Tips and Tricks" by Chris Krueger on September 28 2010
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ConnectWise SIEM (formerly Perch) offers threat detection and response backed by an in-house Security Operations Center (SOC). Defend against business email compromise, account takeovers, and see beyond your network traffic. Our team of threat analysts does all the tedium for you, eliminating the noise and sending only identified and verified treats to action on. Built with multi-tenancy, ConnectWise SIEM helps you keep clients safe with the best threat intel on the market.
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Verilog 2005 synthesizable subset parser built on ANTLR framework. 3-nov-2014: latest release here: https://github.com/gburdell/parser
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The RegWorks(TM) is a set of tools intended to automate the process of register class creation directly from the design specification. It can also be used with other third party tools such as Synopsys RAL or equivalent.
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An online SSL (128-bit strong encryption) repository for scripts created and maintained by Synopsys Design Consultants.
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