Search Results for "hdl" - Page 2
Sort By:
Showing 59 open source projects for "hdl"
View related business solutions-
ConnectWise PSA (formerly Manage) allows you to stop working in separate systems, and helps you build a more profitable business. No more duplicate data entries, inefficient employees, manual invoices, and the inability to accurately track client service issues. Get a behind the scenes look into the award-winning PSA that automates processes for each area of business: sales, help desk, support, finance, and HR.
-
When it comes to cybersecurity, what your clients don’t know can really hurt them. And believe it or not, keep them safe starts with asking questions. With ConnectWise Identify Assessment, get access to risk assessment backed by the NIST Cybersecurity Framework to uncover risks across your client’s entire business, not just their networks. With a clearly defined, easy-to-read risk report in hand, you can start having meaningful security conversations that can get you on the path of keeping your clients protected from every angle. Choose from two assessment levels to cover every client’s need, from the Essentials to cover the basics to our Comprehensive Assessment to dive deeper to uncover additional risks. Our intuitive heat map shows you your client’s overall risk level and priority to address risks based on probability and financial impact. Each report includes remediation recommendations to help you create a revenue-generating action plan.
-
1
PHDL
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic... -
2
JavaRock is a project to develop a compiler from java to vhdl, which enables hardware design by java. Developping JavaRock is over, and the project continues in Synthesijer http://synthesijer.sourceforge.net . Like JavaRock, Synthesijer also aims to develop a compiler from Java to VHDL, which enables hardware design by Java. In addition, Synthesijer generates Verilog HDL and aims to implement advanced features such as optimization, graphical tools, and so on.
-
3
Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.
-
4
Low latency trading platform
The documents for my achievements of the low latency technology
.... Altera OpenCL (on going, just for academic research) OpenCL/Perl/Bat/C++/DDR2/Ethernet/UcOS/Nios II/ Make modification of the Alter OpenCL SDK except the OpecCL C to HDL synthesis to use Ethernet to communicate between Host and Kernel. Rewrite the perl command lines to meet special aims. Monte Carlo Black Schole simulation and QuantLib based on OpenCL standard. -
This means every device on your network, and every interface on every device is automatically analyzed for performance, errors, QoS, and configuration.
-
5
HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL
-
6
VPreproc
C++ Verilog macro preprocessor
This is a standalone preprocessor for the Verilog HDL language. It is modified from the Verilog-PreProcessor of Verilog Perl tool 3.314. Most of the code is written by the team led by Wilson Snyder. What I have done in this project: * Provide a standalone command line interface (without Perl). * Replace the parts implemented in Perl to C++. * Encapsulate the package in a separated namespace for better independence. What I may do in the future: * Replace the C language features to C... -
7
This project includes a set of tools and guidelines designed for rapid production of large-scale embedded systems projects. The tools enable quick generation of reusable, reconfigurable hardware, using a user-specified hardware description language.
-
8
SADDL - Simple Analog and Digital Descirption Language (Project Name subject to change) A BYU project to create a new Hardware Description Language (HDL) that maps out Printed Circuit Boards (PCB's).
-
9
Endit is a text editor mean to HDL source code writing and hacking, like Verilog and VHDL. It integrated a open source verilog compiler , Icarus verilog compiler, in it which is also an excellent open source verilog compiler.
-
Out-of-the-box scripts. Around-the-clock monitoring. Unmatched automation capabilities. Start doing more with less and exceed service delivery expectations.
-
10
A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.
-
11
This Eclipse Plugin invoke Simulation, Synthesis and Place&Route tools from various Vendors for HDL (VHDL/Verilog) development.
-
12
The HDL Complexity Tool parses large complex hardware projects' source code to produce useful complexity results. GOALS: 1)Practical, effective and simple 2) Integrates with existing design flows 3) Used on real projects 4) Based on existing research
-
13
This is a Viterbi HDL Code Generator (VHCG). It can generate the Verilog HDL codes of some kind of Viterbi Decoder which is scalable and parameterized. In-place-state-metric-storage is used in these decoders. I purpose that it can reduce repeated works i
-
14
This tool produces complexity metrics for any language including: SLOC, McCabe, data flow and module hierarchy. It is a derivative of the HDL Complexity Tool: http://hct.sourceforge.net.
-
15
s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.
-
16
OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.
-
17
Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. ZhangDong & KangCai
-
18
VCD is a open format described in the Verilog HDL LRM. This format is widely used by VLSI engineers to exchange design description & data. The aim of the s/w here is to build a library of routines to parse and edit this format.
-
19
Sister is high-level synthesizer for SoC design . It analyzes SystemC(based on C++ language) source code and creates Verilog HDL source code.
-
20
HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
-
21
F- is an ANSish Forth that uses a VM generator to compile Forth into C-based VM suitable for living in a C-based (or assembly or HDL) microcontroller project. The VM supplies 32-bit math, I/O, multitasking and debugger in a ROM footprint as small as 4kB.
-
22
Parallelsimu provides interfaces for parallel simulation of RTL descriptions of complex hardware designs(SoCs, CPUs and etc.) written in Verilog HDL.
-
23
libLCS is a hardware description library in C++ aiming to be as powerfull and easy as the Verilog HDL. It currently supports logic gates, flipflops, clock, and facilitates delays, continuous assignments and variable value dumping into VCD files.
-
24
The Register Description Language (RDL) is an object modeling language used to specify and implement software accessible hardware registers and memories. A RDL compiler can create synthesizable HDL, documentation, driver code, system-c models, and more.
-
25
A custom ALU will be designed using Verilog HDL. The ALU will perform addition, subtraction, multiplication, division, mod, and square root.